This invention relates to integrated circuits (IC""s), and more particularly to electro-static-discharge (ESD) protection circuits.
Improvements in semiconductor processes are producing smaller and smaller transistors and other integrated devices. Unfortunately, the miniaturization of these devices also increases their risk of damage by static electricity. Relatively small electric shocks that might not be noticed by a human can melt or otherwise destroy tiny structures in an integrated transistor.
The input and output pads of an integrated circuit (IC) chip are typically outfitted with protection devices specifically designed to shunt electro-static-discharges (ESD). These ESD-protection devices are effective when the ESD pulse is applied to an input or output (I/O) pin when the ground pin is connected to a ground. During testing for ESD-protection, an ESD test machine applies a positive or negative test to the device-under-test (DUT) with its pins configured in various combinations (see JESD22-A114-B for details). This can include a zap to an I/O pin while the ground pin is connected to the ESD machine as a ground.
Since an actual electric shock can occur between any two pins on a chip, full ESD testing usually includes applying an ESD pulse between every possible combination of two pins. Other pins of the chip can be left floating.
Since the ESD-protection devices are often designed to shunt ESD current from a pin to a power or ground bus, when the ground is floating the ESD-protection device may not work optimally. For example, when an ESD pulse is applied between two different I/O pins, and the power and ground pins are left floating, the ESD current must somehow travel from the one I/O pin to the other I/O pin. Often an indirect path carries the ESD pulse, such as an internal ground bus.
Such I/O-pin to I/O-pin ESD testing can be the most difficult test to pass, especially for Bus-Switch-type products. While xe2x80x9cnormalxe2x80x9d I/O-pin to ground or I/O-pin to power tests may pass, ESD pulses between two I/O pins with the ground pin floating may cause damage. This damage can sometimes result in leakage on a pin after the ESD test.
FIG. 1 is a diagram of a prior-art chip with grounded ESD-protection devices on each I/O pin. Pin A and pin B are I/O pins on an IC chip. Pins A and B are connected by bus-switch transistor 10 which forms a connecting channel when its gate is driven high by inverter 18. When enable EN is high, inverters 16, 18 drive the gate of bus-switch transistor 10 high, connecting pins A, B. When EN is low, transistor 10 isolates pin A from pin B.
ESD protection device 12 is connected to pin A. A wide variety of ESD protection devices could be used. ESD protection device 12 includes structures to shunt an ESD pulse from pin A to an internal ground bus. The shunt could be provided by a large diode to ground, or by a large grounded-gate n-channel transistor (either thin gate oxide or field oxide gate could be used), or by some other structure.
When an ESD pulse is applied to pin A, and the ground pin is grounded, ESD protection device 12 shunts the ESD pulse to the internal ground, and then to the ground pin and back to the ESD tester (or other common ground). ESD protection device 12 protects bus-switch transistor 10 from damage by the ESD pulse.
Pin B is likewise protected by ESD protection device 14. During normal operation in a real system, when EN is low and bus-switch transistor 10 isolated pins A, B, ESD protection device 12 can shunt any shock applied to pin A to the internal ground. This prevents the shock from being coupled to pin B, which may be coupled to another active bus. Such shocks can occur during hot-swapping of PC or network cards.
ESD-Protection Can Fail When Internal Ground Floatsxe2x80x94FIG. 2
While ESD protection devices 12, 14 provide good protection when the internal ground is connected to an external ground, protection can be poor when the internal ground is floating. FIG. 2 highlights failure of ESD-protection devices when the internal ground is floating. In this I/O-pin to I/O-pin ESD test the power and ground pins are left floating. The ESD machine is connected between pin A and pin B. The ESD pulse is applied to pin A while pin B is grounded. All other pins, including power and ground, are left floating.
The ESD pulse applied to pin A charges up any capacitances on pin A until a high enough voltage is reached so the ESD protection device 12 snapbacks. Then the ESD pulse charges internal ground bus 20. Internal ground bus 20 connects to other ESD protection devices including ESD protection device 14 for the grounded pin B. The ESD pulse then travels forward through ESD protection device 14 to reach pin B.
Internal ground bus 20 has some resistance, as does ESD protection device 14 and especially ESD protection device 12, which has to snapback before conduction occurs. The total potential drop in this discharge path can be equal to the sum of the Holding voltage of protection device 12 plus the IR drop across internal ground Bus 20 plus the forward voltage of protection device 14.
The rise in voltage on pin A is coupled to the gate of bus-switch transistor 10 by overlap capacitance 22. Overlap capacitance 22 includes the gate-to-drain overlap capacitance of bus-switch transistor 10, and may include other parasitic capacitances. Since other pins are floating during the ESD test, EN is floating, and inverter 18 does not drive the gate.
The rise in voltage of pin A is thus coupled to the gate of bus-switch transistor 10 by overlap capacitance 22. Once the gate voltage rises to more than a threshold above the source voltage of pin B, bus-switch transistor 10 turns on. The ESD pulse then has a more direct path from pin A to pin B.
Since bus-switch transistor 10 is often a large transistor to decrease the on resistance between pins A, B, the channel resistance of bus-switch transistor 10 may be less than the resistance of the path through internal ground bus 20 and ESD protection devices 12, 14. Then most of the ESD current is carried through bus-switch transistor 10. Since bus-switch transistor 10 may not be designed for such as high current, damage may result.
To prevent such damage, bus-switch transistor 10 can have a more rugged design. For example, the source and drain contacts can be moved farther from the gate edge, and a larger channel length can be used. However, these design changes can increase the capacitance and on resistance, which is undesirable. Even with these design changes, bus-switch transistor 10 may still fail the I/O-pin to I/O-pin ESD test.
FIG. 3 shows ESD-protection devices in more detail. Bus-switch transistor 10 has its gate driven by inverters 16, 18 and connects to I/O pins A, B. Pin A is protected by n-channel transistor 50, which turns on when its gate is pulled high by an ESD pulse on pin A that is coupled through capacitor 54. Resistor 56 discharges the gate of transistor 50 once the ESD event ends.
For pin B, protection is provided by n-channel transistor 60, which turns on when its gate is pulled high by an ESD pulse on pin B that is coupled through capacitor 64. Resistor 66 discharges the gate of transistor 60 once the ESD event ends.
The bulk node or p-type substrates of transistors 10, 50, 60 are usually connected together and to the metal ground bus. Since ground may float during a pin-to-pin ESD test, the p-substrate under transistors 10, 50. 60 also floats. The metal ground bus and bulk node (p-substrate) are connected to the ground pin of chip which floats during the pin-to-pin ESD test.
FIG. 4 shows ESD-protection devices on a chip with a substrate bias. Some integrated circuits use a substrate bias to improve transistor characteristics. For example, the p-substrate can be pumped to a voltage below ground, such as xe2x88x922 or xe2x88x923 volts during normal operation. However, when power is not applied, such as during an ESD test, substrate bias generator 21 is not operating and the p-substrate under transistors 10, 50, 60 is again left floating. Additional problems may develop during ESD testing since the connecting substrate paths may be more complicated due to substrate bias generator 21. The metal ground bus is connected to the ground pin of chip which floats during the pin-to-pin ESD test. The p-substrate is driven by the on-chip substrate charge pump and is not connected to any chip pin and thus floats during the ESD test.
FIG. 5 shows bidirectional cross-grounding ESD protection for a bus-switch transistor. A cross-coupled ESD-protection device is disclosed in xe2x80x9cPin-to-Pin ESD-Protection Structure Having Cross-Pin Activationxe2x80x9d, Ser. No. 10/063,622, filed May 3, 2002 by Tong et al.
Pins A and B are connected by the channel of bus-switch transistor 10, which has a gate driven by inverter 18, which inverts an enable signal EN that is first inverted by inverter 16. Capacitor 54, resistor 56, shunting transistor 50, and cross-grounding transistor 58 protect bus-switch transistor 10 when an ESD pulse is applied to pin A with respect to pin B (an I/O-to-I/O ESD zap configuration). Gate node XAB turns on both transistors 50, 58 when the ESD pulse is applied to pin A with respect to pin B.
For the reverse ESD test, the positive ESD pulse is applied to pin B, and pin A is grounded. Then capacitor 64 charges reverse gate node XBA with a portion of the ESD zap applied to pin B. Before resistor 66 discharges reverse gate node XBA, cross-grounding transistor 68 turns on, connecting grounded pin A to the internal ground bus and substrate taps. The metal ground bus and bulk node (p-substrate) are connected to the ground pin of chip, which floats during the pin-to-pin ESD test.
N-channel shunting transistor 60 also has its gate driven high since its gate is also reverse gate node XBA. The ESD pulse on pin B is shunted to the internal ground through the snapback of n-channel shunting transistor 60 and then through forward-conducting n-channel transistor 50 to the grounded pin A.
The internal ground bus can rise in voltage above the grounded pin A, even when cross-grounding transistor 68 is on. However, the rise in voltage of the internal ground bus is much less than if it were left floating. The internal ground bus is still sufficiently xe2x80x9cgroundedxe2x80x9d even though it may be some voltage above the absolute ESD ground on pin A. ESD protection is still improved because the bulk of the ESD current is discharged through forward conducting n-channel transistor 50.
What is desired is improved ESD protection. Better ESD protection is desired for I/O-pin to I/O-pin ESD tests when ground is floating. ESD protection is desired for integrated circuits that use a substrate bias. An isolation circuit for a bus-switch transistor with a substrate bias is desired that is activated during I/O-pin to I/O-pin ESD tests or similar conditions.